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职位名称 职位类型 工作地点 操作

Description：

Assist PMO to lead company product management functions. Assist product marketing to develop and implement product strategy. Monitor and analyze product development activity against goal. Responsibilities including:

  • Effectively manage all aspects of product development through product life cycle from business feasibility to mass production.
  • Coordinate with Product Marketing to collect market requirements from end-users and the competitive environment, synthesize these requirements into product plan.
  • Support Project Management to define project execution plans and then work with the product development team to ensure quality delivery according to plan.
  • Working with cross functional R&D teams to solve engineering issues during new product development.
  • Support Business Development and sales for all necessary business related activities.
  • Assist PMO to optimize product development flow and continues improvement plan.

Requirements:

1. Bachelor’s degree (or above) in Electrical Engineering or Business with > 5 years related experience

2. Solid understanding of SoC/IC design and manufacturing flow.

3. Professional written and verbal communication and interpersonal skills. Ability to facilitate cross functional group meetings.

4. Team player with strong accountability.

5. Experience of Product Marketing in IC industry is preferred

6. Experience of New Product Introduction or project management in IC industry preferred

Job Description:   

1. Work with SOC architecture team which has very large scale SOC experience from AMD/Intel/Marvell.

2. SOC micro architecture design according to MRD; SOC micro architecture analysis, optimization and simulation.

3. PCIE architecture design and system solution exploration.

4. PCIE3.0/4.0/5.0 controller and phy micro architecture design and optimization.

5. Chip interconnect design based on CXL or CCIX.

6. Read and understand the third-party IP datasheet, finish the IP integration design and RTL coding.

7. Perform RTL code quality check，CDC check，deliver the SDC & UPF file and support the IP/subsystem implementation.

8. Perform RTL-to-Netlist implementation using in-house implementation flow.

9. Function safety (Fusa) definition. Finish FSR, HSR, FMEA and FMEDA.

10. Co-work with DFT team to finish the test related logic implementation based on the IP requirement and support the test pattern development/verification.

11. Support the driver development of the software team, co-work with software team and system to finish the multimedia subsystem related system validation.


Job Requirements: 


1. Hand on experience of logic design.

2. Be familiar with Frontend design & implementation flow，Such as：Lint，CDC check，logic synthesis，formal；Be familiar with related EDA tools.

3. Familiar with scripts (tcl, perl, makefile etc.).

4. Experience of PCIE3.0/4.0/5.0 protocal is a plus.

5. Experience of PCIE controller or phy design is a plus.

6. Experience of PCIE performance optimization is a plus.

7. Experience of CXL or CCIX is a plus.

8. Experience of clock/reset design is a plus.

9. Experience of low power design is a plus; be familiar with DVFS and power gating.

10. Experience of Fusa design is a plus.

11. Teamwork, A high-level of self-motivation and a proactive approach to solving problems.

Job Description:   

1. Work with SOC architecture team which has very large scale SOC experience from AMD/Intel/Marvell.

2. SOC micro architecture design according to MRD; SOC micro architecture analysis, optimization and simulation.

3. PCIE architecture design and system solution exploration.

4. PCIE3.0/4.0/5.0 controller and phy micro architecture design and optimization.

5. Chip interconnect design based on CXL or CCIX.

6. Read and understand the third-party IP datasheet, finish the IP integration design and RTL coding.

7. Perform RTL code quality check，CDC check，deliver the SDC & UPF file and support the IP/subsystem implementation.

8. Perform RTL-to-Netlist implementation using in-house implementation flow.

9. Function safety (Fusa) definition. Finish FSR, HSR, FMEA and FMEDA.

10. Co-work with DFT team to finish the test related logic implementation based on the IP requirement and support the test pattern development/verification.

11. Support the driver development of the software team, co-work with software team and system to finish the multimedia subsystem related system validation.


Job Requirements: 


1. Hand on experience of logic design.

2. Be familiar with Frontend design & implementation flow，Such as：Lint，CDC check，logic synthesis，formal；Be familiar with related EDA tools.

3. Familiar with scripts (tcl, perl, makefile etc.).

4. Experience of PCIE3.0/4.0/5.0 protocal is a plus.

5. Experience of PCIE controller or phy design is a plus.

6. Experience of PCIE performance optimization is a plus.

7. Experience of CXL or CCIX is a plus.

8. Experience of clock/reset design is a plus.

9. Experience of low power design is a plus; be familiar with DVFS and power gating.

10. Experience of Fusa design is a plus.

11. Teamwork, A high-level of self-motivation and a proactive approach to solving problems.

Job Description:   

1. Work with SOC architecture team which has very large scale SOC experience from AMD/Intel/Marvell.

2. SOC micro architecture design according to MRD; SOC micro architecture analysis, optimization and simulation.

3. PCIE architecture design and system solution exploration.

4. PCIE3.0/4.0/5.0 controller and phy micro architecture design and optimization.

5. Chip interconnect design based on CXL or CCIX.

6. Read and understand the third-party IP datasheet, finish the IP integration design and RTL coding.

7. Perform RTL code quality check，CDC check，deliver the SDC & UPF file and support the IP/subsystem implementation.

8. Perform RTL-to-Netlist implementation using in-house implementation flow.

9. Function safety (Fusa) definition. Finish FSR, HSR, FMEA and FMEDA.

10. Co-work with DFT team to finish the test related logic implementation based on the IP requirement and support the test pattern development/verification.

11. Support the driver development of the software team, co-work with software team and system to finish the multimedia subsystem related system validation.


Job Requirements: 


1. Hand on experience of logic design.

2. Be familiar with Frontend design & implementation flow，Such as：Lint，CDC check，logic synthesis，formal；Be familiar with related EDA tools.

3. Familiar with scripts (tcl, perl, makefile etc.).

4. Experience of PCIE3.0/4.0/5.0 protocal is a plus.

5. Experience of PCIE controller or phy design is a plus.

6. Experience of PCIE performance optimization is a plus.

7. Experience of CXL or CCIX is a plus.

8. Experience of clock/reset design is a plus.

9. Experience of low power design is a plus; be familiar with DVFS and power gating.

10. Experience of Fusa design is a plus.

11. Teamwork, A high-level of self-motivation and a proactive approach to solving problems.

Job Description:   

1. ADAS algorithm study and provide implement solution.

2. NPU micro architecture design according to PRD;

3. NPU micro architecture analysis, optimization and simulation.

4. NPU performance/power simulation and optimization.

5. NPU IP integration design and RTL coding;

6. NPU clock/reset architecture design, clock jitter assessment for high speed interface.

7. NPU low power architecture design.

8. Perform RTL code quality check，CDC check，deliver the SDC & UPF file and support the IP/subsystem implementation;

9. Perform RTL-to-Netlist implementation using in-house implementation flow;

10. Function safety (Fusa) definition. Finish FSR, HSR, FMEA and FMEDA.

11. Co-work with DFT team to finish the test related logic implementation based on the IP requirement and support the test pattern development/verification；

12. Support the driver development of the software team, co-work with software team and system to finish the multimedia subsystem related system validation；


Job Requirements: 

1.  Hand on experience of logic design；

2.   Be familiar with Frontend design & implementation flow，Such as：Lint，CDC check，logic synthesis，formal；Be familiar with related EDA tools；

3.  Familiar with scripts (tcl, perl, makefile etc.)

4.  Experience of NPU design is a plus；

5.  Experience of ADAS algorithm is a plus;

6.  Experience of NPU performance optimization is a plus;

7.  Experience of clock/reset design is a plus;

8.  Experience of low power design is a plus; be familiar with DVFS and power gating.

9.  Experience of Fusa design is a plus；

10. Teamwork, A high-level of self-motivation and a proactive approach to solving problems；

Job Description:   

1. ADAS algorithm study and provide implement solution.

2. NPU micro architecture design according to PRD;

3. NPU micro architecture analysis, optimization and simulation.

4. NPU performance/power simulation and optimization.

5. NPU IP integration design and RTL coding;

6. NPU clock/reset architecture design, clock jitter assessment for high speed interface.

7. NPU low power architecture design.

8. Perform RTL code quality check，CDC check，deliver the SDC & UPF file and support the IP/subsystem implementation;

9. Perform RTL-to-Netlist implementation using in-house implementation flow;

10. Function safety (Fusa) definition. Finish FSR, HSR, FMEA and FMEDA.

11. Co-work with DFT team to finish the test related logic implementation based on the IP requirement and support the test pattern development/verification；

12. Support the driver development of the software team, co-work with software team and system to finish the multimedia subsystem related system validation；

Job Requirements: 

1.  Hand on experience of logic design；

2.   Be familiar with Frontend design & implementation flow，Such as：Lint，CDC check，logic synthesis，formal；Be familiar with related EDA tools；

3.  Familiar with scripts (tcl, perl, makefile etc.)

4.  Experience of NPU design is a plus；

5.  Experience of ADAS algorithm is a plus;

6.  Experience of NPU performance optimization is a plus;

7.  Experience of clock/reset design is a plus;

8.  Experience of low power design is a plus; be familiar with DVFS and power gating.

9.  Experience of Fusa design is a plus；

10. Teamwork, A high-level of self-motivation and a proactive approach to solving problems；

Job Description:

1. ADAS algorithm study andprovide implement solution.

2. NPU micro architecture design according to PRD;

3. NPU micro architecture analysis, optimization and simulation.

4. NPU performance/power simulation and optimization.

5. NPU IP integration design and RTL coding;

6. NPU clock/reset architecture design, clock jitter assessment forhigh speed interface.

7. NPU low power architecture design.

8. Perform RTL code quality check，CDC check，deliver the SDC & UPF file and support the IP/subsystemimplementation;

9. Perform RTL-to-Netlist implementation using in-house implementationflow;

10. Function safety (Fusa) definition. Finish FSR, HSR, FMEA and FMEDA.

11. Co-work with DFT team to finish the test related logicimplementation based on the IP requirement and support the test patterndevelopment/verification；

12. Support the driver development of the software team, co-work withsoftware team and system to finish the multimedia subsystem related systemvalidation；

JobRequirements:

1. Hand on experience of logicdesign；

2. Be familiar with Frontend design & implementation flow，Such as：Lint，CDCcheck，logic synthesis，formal；Be familiar with related EDA tools；

3. Familiar with scripts (tcl, perl, makefile etc.)

4. Experience of NPU design is a plus；

5. Experience of ADAS algorithm is a plus;

6. Experience of NPU performance optimization is a plus;

7. Experience of clock/reset design is a plus;

8. Experience of low power design is a plus; be familiar with DVFS andpower gating.

9. Experience of Fusa design is a plus；

10. Teamwork, A high-level of self-motivation and a proactive approachto solving problems；

职位描述：

1. 与经验丰富的设计团队合作，为汽车SoC, MPU和MCU设计模拟集成电路

2. 负责模拟集成电路设计、仿真、布局布线、流片和芯片回片后的功能验证。

3. 主要设计GPIO、ADC、DAC、稳压器（DCDC或LDO）、OSC、PLL等车规高可靠性的模拟IP。

4. 与市场产品团队密切合作，支持产品的成功发布。

5. 自我激励，积极进取，努力工作。

 

职位要求：

1. 集成电路/电子工程专业，硕士或以上学历

2. 熟悉模拟电路

职位描述：

1. 与经验丰富的设计团队合作，为汽车SoC, MPU和MCU设计模拟集成电路

2. 负责模拟集成电路设计、仿真、布局布线、流片和芯片回片后的功能验证。

3. 主要设计GPIO、ADC、DAC、稳压器（DCDC或LDO）、OSC、PLL等车规高可靠性的模拟IP。

4. 与市场产品团队密切合作，支持产品的成功发布。

5. 自我激励，积极进取，努力工作。

 

职位要求：

1. 集成电路/电子工程专业，硕士或以上学历

2. 熟悉模拟电路

职位描述：

1. 与经验丰富的设计团队合作，为汽车SoC, MPU和MCU设计模拟集成电路

2. 负责模拟集成电路设计、仿真、布局布线、流片和芯片回片后的功能验证。

3. 主要设计GPIO、ADC、DAC、稳压器（DCDC或LDO）、OSC、PLL等车规高可靠性的模拟IP。

4. 与市场产品团队密切合作，支持产品的成功发布。

5. 自我激励，积极进取，努力工作。

 

职位要求：

1. 集成电路/电子工程专业，硕士或以上学历

2. 熟悉模拟电路

职位描述：

与前端设计团队和物理设计团队合作，完成从RTL到GDS的汽车SoC芯片物理实现。专注于深亚微米超大集成电路芯片的物理设计，包括模块和芯片级综合、floorplan自动布局布线、时序收敛、物理验证、EM/IR签核检查等。

 

职位要求：

1.集成电路/电子工程相关专业，硕士或以上学历

2.数字集成电路知识

具备以下领域的扎实知识者优先：

1）具备ASIC数字版图流程知识

2）熟悉Python/Tcl和Unix/Linux Makefile脚本编写

职位描述：

与前端设计团队和物理设计团队合作，完成从RTL到GDS的汽车SoC芯片物理实现。专注于深亚微米超大集成电路芯片的物理设计，包括模块和芯片级综合、floorplan自动布局布线、时序收敛、物理验证、EM/IR签核检查等。

 

职位要求：

1.集成电路/电子工程相关专业，硕士或以上学历

2.数字集成电路知识

具备以下领域的扎实知识者优先：

1）具备ASIC数字版图流程知识

2）熟悉Python/Tcl和Unix/Linux Makefile脚本编写

职位描述：

与前端设计团队和物理设计团队合作，完成从RTL到GDS的汽车SoC芯片物理实现。专注于深亚微米超大集成电路芯片的物理设计，包括模块和芯片级综合、floorplan自动布局布线、时序收敛、物理验证、EM/IR签核检查等。

 

职位要求：

1.集成电路/电子工程相关专业，硕士或以上学历

2.数字集成电路知识

具备以下领域的扎实知识者优先：

1）具备ASIC数字版图流程知识

2）熟悉Python/Tcl和Unix/Linux Makefile脚本编写

职位描述：

作为MPD团队数字设计工程师，负责下一代先进的汽车MPU和MCU芯片组设计, 职责包括但不限于

1. 参与IP/子系统微架构设计并完成相关文档编写

2. 撰写详细的技术文件，包括规范、框图和具体要求

3. 设计的RTL实现以及相关集成工作

4. 模块级汽车功能安全相关设计和文档创建

5. 提供测试案例，进行第三方IP功能测试

6. 采用sdc/upf进行模块级综合；并协助芯片级综合。

7. 为芯片的bring up提供支持，并协助回片后的芯片性能测试。

8. 协助进行汽车功能安全（ISO26262）认证

9. 定义时序和功耗规格，并提供时序解决方案。

10. 协助后端同事分析时序和后端实现方案


职位要求：

1. 集成电路/电子工程/计算机科学与技术相关专业，硕士及以上学历

2. 良好的C、Verilog、SystemVerilog经验

具备以下领域的知识者优先：

1) 熟悉ARM cortex M or cortex R

2) 具备CAN_FD/LIN/USB/Ethernet/UFS/eMMC/EFALSH控制器的知识或设计经验。

3）熟悉Python/Tcl和Unix/Linux Makefile脚本编写

职位描述：

作为MPD团队数字设计工程师，负责下一代先进的汽车MPU和MCU芯片组设计, 职责包括但不限于

1. 参与IP/子系统微架构设计并完成相关文档编写

2. 撰写详细的技术文件，包括规范、框图和具体要求

3. 设计的RTL实现以及相关集成工作

4. 模块级汽车功能安全相关设计和文档创建

5. 提供测试案例，进行第三方IP功能测试

6. 采用sdc/upf进行模块级综合；并协助芯片级综合。

7. 为芯片的bring up提供支持，并协助回片后的芯片性能测试。

8. 协助进行汽车功能安全（ISO26262）认证

9. 定义时序和功耗规格，并提供时序解决方案。

10. 协助后端同事分析时序和后端实现方案


职位要求：

1. 集成电路/电子工程/计算机科学与技术相关专业，硕士及以上学历

2. 良好的C、Verilog、SystemVerilog经验

具备以下领域的知识者优先：

1) 熟悉ARM cortex M or cortex R

2) 具备CAN_FD/LIN/USB/Ethernet/UFS/eMMC/EFALSH控制器的知识或设计经验。

3）熟悉Python/Tcl和Unix/Linux Makefile脚本编写

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